1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a circuit for compensating for a phase in data input to the semiconductor memory device.
2. Description of the Background Art
A synchronous dynamic random access memory (SDRAM) operating at high speed receives an external control signal, an address signal and write data, in synchronism with an external clock signal, and outputs read data.
Here, a "single data rate" and a "double data rate" will be described with respect to write data reception.
FIGS. 13A and 13B are timing charts illustrating reception of an external data signal EXTD at a "single data rate". As shown in FIGS. 13A and 13B, at the "single data rate" external data signal EXTD shown in FIG. 13B is received in synchronism with a rising edge of an external clock signal EXTCLK shown in FIG. 13A. Therefore, external data signal EXTD is received once in a clock cycle tC of external clock signal EXTCLK.
FIGS. 14A and 14B are timing charts illustrating an example of reception of external data signal EXTD at the "double data rate". As shown in FIGS. 14A and 14B, at the "double data rate" external data signal EXTD shown in FIG. 14B is obtained in synchronism with rising and falling edges of external clock signal EXTCLK shown in FIG. 14A. Therefore, external data signal EXTD is received twice in a clock cycle tC of external clock signal EXTCLK.
FIGS. 15A and 15B are timing charts illustrating another example of reception of external data signal EXTD at the "double data rate".
In this example of the "double data rate", external data signal EXTD shown in FIG. 15B is received twice in a clock cycle tC of external clock signal EXTCLK in synchronism with a rising edge of external clock signal EXTCLK shown in FIG. 15A and also with an edge of a clock signal (not shown) generated inside a device in synchronism with the rising edge and shifted a half period (1/2.multidot.tC) from external clock signal EXTCLK.
Since the SDRAM receives the external control signal, the address signal and the write data in synchronism with the external clock signal as described above, higher speed of the SDRAM operation due to higher frequency of the external clock signal causes a skew between the external clock signal and each of external control signal, address signal and the write data. Referring to FIGS. 16A to 16D, reduction in setup time and hold time will be described with respect to the "double data rate" shown in FIGS. 15A and 15B. The setup time refers to the time from the start of an effective (valid) state allowing data reception until actual data reception (a data reception edge) and the hold time is from the data reception edge to the end of the valid state.
Generally, a memory controller outputs write data in synchronism with a synchronized signal. Since this output write data experiences a mismatch between impedance on a board and that on a memory card before it reaches an SDRAM device from the memory controller, it causes a skew due to difference in transfer delay time of the write data and the external clock signal which are input to the same SDRAM device. Therefore, in the SDRAM device, external input data is valid in the external data reception cycle (1/2.multidot.tC) minus skew time due to transfer delay.
Let us consider the data reception from the outside to the inside of the device, from the view point of internal device operation. An internal clock signal INTDCLK shown in FIG. 16C which is generated by doubling the frequency of the external clock signal shown in FIG. 16A and internal write data INTD received into the device and shown in FIG. 16D cause an undesirable skew. The skew is further increased by characteristics of a clock signal input buffer receiving the external clock signal into the device, a data input buffer receiving external data into the device, a frequency doubler generating internal clock signal INTDCLK by doubling the frequency of the external clock signal which is input to the clock signal input buffer, and so on. Therefore, setup/hold time of internal write data INTD with respect to internal clock signal INTDCLK would be shorter when the device operates at higher frequency.